A known means of establishing frame and word synchronization in serial data transmission is to use one, or perhaps a few, binary synchronization word patterns at the beginning of a serial data message. By careful choice of word patterns, the synchronization word patterns are typically resistant to noise falsing while also offering better probability of detection than portions of message contents which follow. Multiple patterns are used to indicate fundamental information about the signal which follows, such as the data rate. This is often accomplished by using pairs of synchronization words which are the binary inverse of each other. In the serial data receiver, such as a portable selective call receiver, the correct synchronization pattern or patterns are then compared to each successive received bit pattern of the same length as the synchronization word, and synchronization is detected when the mismatch between a correct synchronization pattern and a successive received bit pattern is less than a predetermined number of bits. For example, a 32 bit long synchronization word may be used, with the predetermined number of mismatched errors being three, thereby allowing synchronization detection with up to two bit errors.
The same detection process is also used with other data words wherein the data word contents are predetermined in each receiver, such as a serial data receiver identification word. The length of the word is made long enough to permit the selection of an error code which provides sufficient Hamming distance between all the predetermined identification numbers used within a system, such as in a POCSAG (Post Office Code Standard Advisory Group) system, thereby avoiding false identification responses even in the presence of errors.
A known means of such synchronization detection, which has been used successfully, is to use a correlation method in a microprocessor which first performs a binary Exclusive Or operation, on a bit by bit basis, of the bits of each successive received bit pattern with a stored correct synchronization pattern, generating a comparison word from the bits resulting from the Exclusive Or operation, determining the number of ones (mismatching bits) in the comparison word, which is a representation of the weight of the word, and comparing the weight to the predetermined number of mismatched bits. When the inverse pattern is also used, the weight of the inverse pattern, which can be determined from the weight of the pattern, is also compared to the predetermined number of mismatched bits. Because the synchronization word is often longer than the data length of the microprocessor (e.g., 32 bits versus 8 bits), the method often requires a large number of instructions to be performed.
Another means of performing the weight measurement necessary for correlation detection is to use a straightforward combinatorial logic circuit which has an AND function for each allowable comparison word. For example, in the case where the synchronization word is 32 bits long and where up to two errors are allowed, there are 529 different allowable words, resulting in the equivalent of 529 thirty two bit AND gates, thus making this approach impractical due to the number of gates involved to realize such a circuit.
As serial data rates increase, the method of using a microprocessor to detect correlation requires faster and more powerful microprocessors. In portable electronic devices that use serial data communications, the detection of the synchronization word may require the use of a higher current drain or more expensive microprocessor than what would otherwise be needed in the portable electronic devices.
Thus, what is needed is a fast, cost effective, low power means to detect the synchronization word.